? semiconductor components industries, llc, 2002 july, 2002 rev. 1 1 publication order number: nlasb3157/d nlasb3157 2:1 multiplexer the nlasb3157 is an advanced cmos analog switch fabricated with silicon gate cmos technology. it achieves very low propagation delay and rds on resistances while maintaining cmos low power dissipation. analog and digital voltages that may vary across the full powersupply range (from v cc to gnd). this device is a drop in replacement for the nc7sb3157. the select pin has overvoltage protection that allows voltages above v cc, up to 7.0 v to be present on the pin without damage or disruption of operation of the part, regardless of the operating voltage. features ? high speed: t pd = 1.0 ns (typ) at v cc = 5.0 v ? low power dissipation: i cc = 2.0 a (max) at t a = 25 c ? standard cmos logic levels ? high bandwidth, improved linearity ? switches standard ntsc/pal video, audio, spdif and hdtv ? may be used for clock switching, data mux'ing, etc. ? low rds on ? break before make circuitry, prevents inadvertent shorts ? can switch balanced signal pairs, e.g. lvds 200bits/sec ? latchup performance exceeds 300 ma ? pin for pin drop in for nc7sb3157 ? tiny sc88 package only 2.0 x 2.1 mm ? esd performance: hbm 2000 v; mm 200 v figure 1. pinout (top view) select b 1 gnd a b 0 1 2 3 6 4 v cc 5 1 0 sc88/sot363/sc70 df suffix case 419b 1 6 device package shipping ordering information nlasb3157dft2 sc88/sot363/ sc70 tape & reel http://onsemi.com marking diagram af d af = specific device code d = date code l h function table select input function b0 connected to a b1 connected to a
nlasb3157 http://onsemi.com 2 maximum ratings (note 1) rating symbol value unit supply voltage v cc 0.5 to +7.0 v dc switch voltage (note 2) v s 0.5 to v cc + 0.5 v dc input voltage (note 2) v in 0.5 to + 7.0 v dc input diode current @ v in 0 v i ik 50 ma dc output current i out 128 ma dc v cc or ground current i cc /i gnd +100 ma storage temperature range t stg 65 to +150 c junction temperature under bias t j 150 c junction lead temperature (soldering, 10 seconds) t l 260 c power dissipation @ +85 c p d 180 mw recommended operating conditions (note 3) characteristic symbol min max unit supply voltage operating v cc 1.65 5.5 v select input voltage v in 0 v cc v switch input voltage v in 0 v cc v output voltage v out 0 v cc v operating t emperature t a 40 +85 c input rise and fall time control input v cc = 2.3 v3.6 v control input v cc = 4.5 v5.5 v t r , t f 0 0 10 5 ns/v thermal resistance ja 350 c/w 1. maximum ratings are dc values beyond which the device may be damaged or have its useful life impaired. the data sheet specifications sh ould be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input lo ading variables. fairchild does not recommend operation outside data sheet specifications. 2. the input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. 3. select input must be held high or low, it must not float.
nlasb3157 http://onsemi.com 3 dc electrical characteristics v cc t a = +25 c t a = 40 c to +85 c symbol parameter test conditions v cc (v) min typ max min max unit v ih high level input v oltage 1.651.95 2.35.5 0.75 v cc 0.7 v cc 0.75 v cc 0.7 v cc v v il low level input v oltage 1.651.95 2.35.5 0.25 v cc 0.3 v cc 0.25 v cc 0.3 v cc v i in input leakage current 0 v in 5.5 v 05.5 0.05 0.1 1 a i off off state leakage current 0 a, b v cc 1.655.5 0.05 0.1 1 a r on switch on resistance (note 4) v in = 0 v, i o = 30 ma v in = 2.4 v, i o = 30 ma v in = 4.5 v, i o = 30 ma 4.5 8 13 9 12 17 15 14 20 15 v in = 0 v, i o = 24 ma v in = 3 v, i o = 24 ma 3.0 10 12 14 18 18 18 v in = 0 v, i o = 8 ma v in = 2.3 v, i o = 8 ma 2.3 13 15 18 25 22 25 v in = 0 v, i o = 4 ma v in = 1.65 v, i o = 4 ma 1.65 20 20 24 40 30 40 i cc quiescent supply current all channels on or off v in = v cc or gnd i out = 0 5.5 1 10 a analog signal range v cc 0 v cc 0 v cc v r range on resistance over signal range (note 4) (note 8) i a = 30 ma, 0 v bn v cc i a = 24 ma, 0 v bn v cc i a = 8 ma, 0 v bn v cc i a = 4 ma, 0 v bn v cc 4.5 3.0 2.3 1.65 25 50 100 300 r on on resistance match between channels (note 4) (note 5) (note 6) i a = 30 ma, v bn = 3.15 i a = 24 ma, v bn = 2.1 i a = 8 ma, v bn = 1.6 i a = 4 ma, v bn = 1.15 4.5 3.0 2.3 1.65 0.15 0.2 0.5 0.5 r flat on resistance flatness (note 4) (note 5) (note 7) i a = 30 ma, 0 v bn v cc i a = 24 ma, 0 v bn v cc i a = 8 ma, 0 v bn v cc i a = 4 ma, 0 v bn v cc 5.0 3.3 2.5 1.8 6 12 28 125 4. measured by the voltage drop between a and b pins at the indicated current through the switch. on resistance is determined by the lower of the voltages on the two (a or b ports). 5. parameter is characterized but not tested in production. 6. r on = r on max r on min measured at identical v cc , temperature and voltage levels. 7. flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of cond itions. 8. guaranteed by design.
nlasb3157 http://onsemi.com 4 ac electrical characteristics v cc t a = +25 c t a = 40 c to +85 c figure symbol parameter test conditions v cc (v) min typ max min max unit fig u re number t phl t plh propagation delay bus to bus (note 10) v i = open 1.651.95 2.32.7 3.03.6 4.55.5 1.2 0.8 0.3 1.2 0.8 0.3 ns figures 2, 3 t pzl t pzh output enable time turn on time (a to b n ) v i = 2 v cc for t pzl v i = 0 v for t pzh 1.651.95 2.32.7 3.03.6 4.55.5 7 3.5 2.5 1.7 70 32 21 13 7 3.5 2.5 1.7 70 35 23 15 ns figures 2, 3 t plz t phz output disable time turn off time (a port to b port) v i = 2 v cc for t plz v i = 0 v for t phz 1.651.95 2.32.7 3.03.6 4.55.5 3 2 1.5 0.8 13.7 8.1 6.7 6.1 3 2 1.5 0.8 13.8 8.2 7 6.2 ns figures 2, 3 t bm break before make time (note 9) 1.651.95 2.32.7 3.03.6 4.55.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns figure 4 q charge injection (note 9) c l = 0.1 nf, v gen = 0 v r gen = 0 5.0 3.3 7 3 pc figure 5 oirr off isolation (note 11) r l = 50 f = 10 mhz 1.655.5 57 db figure 6 xtalk crosstalk r l = 50 f = 10 mhz 1.655.5 54 db figure 7 bw 3 db bandwidth r l = 50 1.655.5 250 mhz figure 10 thd total harmonic distortion (note 9) r l = 600 0.5 v pp f = 600 hz to 20 khz 5 0.011 % capacitance (note 12) symbol parameter test conditions typ max unit figure number c in select pin input capacitance v cc = 0 v 2.3 pf c iob b port off capacitance v cc = 5.0 v 6.5 pf figure 8 c ioaon a port capacitance when switch is enabled v cc = 5.0 v 18.5 pf figure 9 9. guaranteed by design. 10. this parameter is guaranteed by design but not tested. the bus switch contributes no propagation delay other than the rc del ay of the on resistance of the switch and the 50 pf load capacitance, when driven by an ideal voltage source (zero output impedance). 11. off isolation = 20 log 10 [v a /v bn ]. 12. t a = +25 c, f = 1 mhz, capacitance is characterized but not tested in production.
nlasb3157 http://onsemi.com 5 t w v cc gnd v oh v ol 50% 10% 10% 50% 50% 90% 90% t f = 2.5 ns t r = 2.5 ns switch input output 50% t phl t plh v cc gnd v tri 50% 10% 10% 50% 50% 90% 90% t f = 2.5 ns t r = 2.5 ns select input output t pzl v tri output 50% t pzh v ol v oh t phz t plz v ol + 0.3 v v oh 0.3 v note: input driven by 50 source terminated in 50 note: c l includes load and stray capacitance note: input prr = 1.0 mhz; t w = 500 ns v i rd ru c l from output under test figure 2. ac test circuit figure 3. ac waveforms figure 4. break before make interval timing logic input v out t d 0.9 v out r l c l v out v in logic input a s b 0 b 1 ac loading and waveforms
nlasb3157 http://onsemi.com 6 figure 5. charge injection test r l 1 m c l 100 pf v out logic input a s b n r gen v ge q = ( v out )(c l ) v out on off off v out logic input figure 6. off isolation figure 7. crosstalk s b n logic input 0 v or v ih 10 nf v cc analyzer a gnd 50 50 s b 0 10 nf v cc analyzer a gnd 50 signal generator 0 dbm 50 b 1 figure 8. channel off capacitance figure 9. channel on capacitance figure 10. bandwidth s b n 10 nf v cc a gnd signal generator 0 dbm 50 logic input 0 v or v cc s b n logic input 0 v or v cc 10 nf v cc a gnd capacitance meter s b n logic input 0 v or v cc 10 nf v cc a gnd capacitance meter f = 1 mhz f = 1 mhz ac loading and waveforms
nlasb3157 http://onsemi.com 7 sc88/sot363/sc70 0.5 mm (min) 0.4 mm (min) 0.65 mm 0.65 mm 1.9 mm user direction of feed at2'' pin one away from sprocket hole 32 dft2 (sc88) reel configuration/orientation
nlasb3157 http://onsemi.com 8 package dimensions sc88/sot363/sc70 df suffix case 419b02 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. 419b-01 obsolete, new standard 419b-02. dim a min max min max millimeters 1.80 2.20 0.071 0.087 inches b 1.15 1.35 0.045 0.053 c 0.80 1.10 0.031 0.043 d 0.10 0.30 0.004 0.012 g 0.65 bsc 0.026 bsc h --- 0.10 --- 0.004 j 0.10 0.25 0.004 0.010 k 0.10 0.30 0.004 0.012 n 0.20 ref 0.008 ref s 2.00 2.20 0.079 0.087 b 0.2 (0.008) mm 123 a g s h c n j k 654 b d 6 pl on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provid ed in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into t he body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nlasb3157/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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